Power saving is one of the most critical topic for cellular modem design. Low power design leads to longer battery life for a mobile device, which is extremely important for good user experience. The power consumption of a cellular modem in a mobile device 100 as exemplarily shown in FIG. 1 usually consists of two major contributors which are RF (radio frequency 101) power consumption 106 and BB (Baseband 103) power consumption 102 from the battery 105. The baseband power is further divided into dynamical power and leakage power. The dynamical power is usually much higher than the leakage power, and is proportionally with Vdd2*fclk where Vdd is the baseband power supply voltage 102 and fclk is the baseband clock frequency 104. fclk and Vdd are correlated such that a high fclk usually requires high Vdd to satisfy the timing requirements in the silicon, for example setup-time and hold-time. In most LTE master scenarios, the baseband clocks with the highest rate are the system clock (sysClk) and control clock (ctrlClk) of the demodulation chain, i.e. inner receiver (IRX) and outer receiver (ORX), their clock settings determine Vdd setting in most scenarios. There is a need to improve power efficiency in the mobile device.